1. Field of the Invention
The present invention generally relates to semiconductor device fabrication and, more particularly, to methods for manufacturing a gate spacer for self-aligned contacts.
2. Description of the Related Art
FIG. 1 is a cross sectional view, illustrating a storage electrode contact hole (18a) and a bit line contact hole (18b), exposing a blanket etch stop layer 11 in a cell array region of a semiconductor memory device, taken along a direction parallel to bit lines (not shown). The storage-electrode contact hole (18a) and a bit line contact hole (18b) are typically formed using a self-aligned contact (SAC) process. Thus, the SAC process can be used for forming contact pads, which in turn form another contact for conductive lines in the subsequent processing steps.
This conventional SAC process uses a hard mask (10) and a gate spacer (14), which are formed of a dielectric material such as silicon nitride having high etching selectivity with respect to an interlayer insulating layer (16) formed of a dielectric material such as oxide. Because the hard mask (10) and the gate spacer (14) are formed of a material having high etching selectivity, i.e. a slower etch rate than the material used for the interlayer insulating layer (16), the SAC process selectively etches the interlayer insulating layer (16) between gate structures at a faster rate than it etches the gate spacer (14) and the hard mask (10). Thus, the contact holes (18a, 18b) can be formed even when a photoresist pattern defining the contact holes is not precisely aligned.
FIG. 2A illustrates the shape of conventional gate spacer (14) formed of a dielectric material such as a silicon nitride, after a self-aligned contact hole 18a is formed in the interlayer insulating layer (16) using the SAC process. As semiconductor devices continuously scale down, very fine patterns are formed in semiconductor devices. Thus, the aspect ratio of contact holes is increased and the etching margin of the SAC process is significantly reduced. Further, the spacing between contact holes is smaller than that between a pair of facing gate electrodes, which results in defects such as pad bridges.
To solve the above-mentioned problems, recently, in the SAC process, a polysilicon layer on the top of a gate stack is removed by a chemical mechanical polishing (CMP) process to separate nodes, as illustrated in FIG. 2B and FIG. 2C.
However, such a SAC process typically requires over-polishing during the CMP process, resulting in a loss of the polysilicon layer as illustrated in FIG. 2C. Additionally, if more polysilicon layer is lost in the subsequent cleaning process, the size of the pad contact hole is further reduced, substantially degrading device characteristics.